CZ-depth optimization

Case Study: Optimizing CZ-Depth for Neutral-Atom Quantum Processors (QuEra)

Hardware-Aware Compilation for Parallel CZ Scheduling

Neutral-atom processors are one of the most promising paths to scaling quantum hardware, but their performance hinges on how efficiently a circuit uses the device's native operations. On these platforms, the cost that matters most is not the raw number of gates, it is how many sequential layers of laser pulses a circuit demands. Every extra layer adds runtime and error. This is where compilation stops being a convenience and becomes a performance lever. Working with QuEra, Classiq built a hardware-aware scheduling capability that reorders circuits to match how neutral-atom hardware actually executes, cutting the laser pulses required to run the same algorithm"

A key hardware metric for these systems is the CZ-depth:

The number of sequential laser operations required to execute all CZ gates in a circuit.

Reducing CZ-depth directly impacts:

• Execution time  
• Accumulated error – in neutral-atom platforms, dominant two-qubit errors scale primarily with the number of entangling layers rather than the number of gates within a layer
• Scalability of depth-sensitive algorithms  

Neutral-atom architectures enable extensive parallel execution of CZ gates under well-defined hardware constraints. Realizing this potential in practice requires scheduling strategies that explicitly account for qubit overlap and commutation structure, aligning circuit ordering with the device’s native execution model.

Classiq developed a hardware-aware CZ scheduling capability that reorders commuting operations to better align circuits with the native execution model of neutral-atom hardware. In representative circuit families, this resulted in measurable reductions in CZ-depth.

Problem Definition: The Gap Between Logical Circuits and Hardware Scheduling

A quantum circuit is typically represented as a linear sequence of gates (logical ordering) or as a directed acyclic graph (DAG) capturing gate dependencies.

On neutral-atom platforms, the constraints are simpler; two CZ gates conflict only if they share a qubit.

However, most DAGs include extra edges because compilers impose artificial ordering:

• Even when gates commute
• Even when intermediate single-qubit operations are only RZ rotations (which preserve commutation)

Thus, the circuit appears to require more sequential layers than truly needed.

Core Insight: Many CZ Gates Commute and Can Be Reordered

The commutation properties of CZ gates are well established in the literature. Here, we leverage these properties explicitly within a hardware-aware scheduling context.

A CZ gate is diagonal in the computational basis, so two CZ operations commute whenever:

1. They act on disjoint qubits, or
2. They share exactly one qubit and that qubit experiences only RZ rotations between the gates.

This rule is formalized as follows:

A pair of CZ gates is swappable if the shared qubit is not manipulated by a non-RZ gate between them.

In practical circuits (QAOA, GHZ preparation, arithmetic), this produces many opportunities for safe reordering.

Classiq’s Hardware-Aware CZ-Depth Optimization Algorithm

This optimization operates at the scheduling layer. It preserves the high-level logical structure of the circuit and focuses on reordering commuting CZ operations to better match the hardware execution model.

Classiq implements a two-stage approach:

Stage 1 — Static Analysis (Commutation & Dependency Extraction)

1. Parse the circuit (QASM or internal IR).
2. Build a full dependency graph.
3. Identify all pairs of CZ gates that:
   
   • Share a qubit and meet the RZ-only constraint
   • Or act on disjoint qubits

These are swappable pairs.

Stage 2 — Guided Reordering Using Simulated Annealing

This optimization explores permutations of commuting CZ gates to minimize CZ-depth:

Algorithm: CZ-Depth Optimization (Simulated Annealing)

1. Randomly select a swappable pair of adjacent CZ gates.
2. Swap the order of the selected gates.
3. Recompute the CZ-depth:
      - Use rapid layering (topological sorting)
      - Count the resulting CZ layers
4. Acceptance rule:
      a. If the new depth is smaller → accept the swap.
      b. Otherwise, accept with probability:
             p = exp(-Δ/T)
         where Δ is the increase in depth, and T is the temperature.
5. Lower the temperature T gradually (cooling schedule) to refine the solution over time.

This technique escapes local minima, produces strictly valid circuits, and handles large circuits efficiently.

CZ-Depth Layering After Reordering

Once a candidate ordering is identified, a final greedy layer construction assigns each CZ gate to the earliest possible parallel layer that does not violate qubit exclusivity.

This is implemented via efficient topological sorting over the reduced dependency graph.

Results on Practical Circuits

Evaluation of Representative Circuit Families

To evaluate the practical impact of hardware-aware reordering, we analyzed representative circuit families and measured the resulting CZ-depth after scheduling.

Application-Specific Families (From QuEra partnership)

The “Savings by Category” study shows:

• 10–40% savings across many circuit categories
  
• Occasionally >40% for structured workloads
  

Integration with QuEra Hardware

This optimization was built explicitly for:

• Parallel CZ architectures
• Laser-pulse scheduling constraints
• Hardware error models based on pulse count

Through discussions with QuEra engineering teams, the following requirements were integrated:

• Emit QASM with reordered CZs
• Keep compilation deterministic where needed
• Preserve algorithmic semantics and orthogonality with other transpilation stages

This positions Classiq as a full-stack partner that understands and exploits hardware-native metrics, not just generic circuit size or depth.

This work is intended to demonstrate how hardware-aware CZ scheduling can be integrated into a high-level synthesis workflow targeting neutral-atom platforms. It complements existing parallelization tools by embedding device-specific scheduling considerations directly into the circuit generation and compilation flow.

Technical and Business Value

For Users & Developers

• Faster circuit execution
• Lower laser exposure → reduced decoherence
• Better scalability for deep variational circuits
• Cleaner alignment with QuEra’s architecture

For Hardware Providers

• Demonstrates the value of hardware-aware compilation
• Provides a pathway to differentiate by exposing novel cost metrics
• Reduces the performance gap between theoretical algorithms and physical execution
  

For Classiq’s HW Solutions Portfolio

This case study showcases Classiq’s ability to:

1. Incorporate custom hardware metrics
2. Extend compiler infrastructure to target specific devices
3. Develop IP-protected optimization

This type of collaboration strengthens Classiq’s position as the platform that bridges algorithm design, automatic synthesis, and hardware-aware optimization.

結論

Neutral-atom architectures provide exceptional native parallelism for CZ gates, but realizing their full potential requires compilers that understand and exploit this structure. Classiq’s CZ-depth optimization— rooted in formal commutation analysis, dependency-graph refinement, and simulated annealing—achieves consistent, substantial reductions in required laser pulses.

Our collaboration with QuEra demonstrates Classiq’s commitment to developing device-aware solutions that leverage hardware characteristics to deliver actionable performance gains. This technology plays a crucial role in Classiq’s Hardware Solutions layer, enabling customers to achieve higher fidelity, shorter runtimes, and improved scalability on state-of-the-art quantum systems.

For a detailed description of QuEra’s execution model and parallelism constraints, see the Bloqade Auto-Parallelism tutorial by QuEra [https://bloqade.quera.com/latest/digital/tutorials/auto_parallelism/ ].